Technical Field
The present invention relates generally to memories and, in particular, to a bad bit register for a memory.
Description of the Related Art
Some multi-time-programmable non-volatile memories, for example Spin Torque MRAM, are plagued by the problem of having an intrinsic write-error-rate. This means that every time any bit is written, there is some non-zero probability that the bit will not write to the correct state. Typically, the error-rate for such errors is engineered to be very low, for example 1e-9 errors/write or less. However, in many applications this is not sufficient, particularly if some bits have worse write-error-rates than other bits. As used herein, the term “bad bit” refers to a bit that has a worse write error rate than other bits, e.g., above a threshold number of other bits and/or above a threshold write error rate. In that case, the bad bits will eventually cause errors in the field.
One way to deal with this problem is to use error correction code, which can correct some forms of errors. For example, some codes can correct for one error in a word of 72 bits, but not for two errors. However, if there are bad bits with sufficiently high write-error-rates, then eventually they will cause an uncorrectable error (for example, two errors in one word).
Another way to deal with this problem is to identify and fuse-out these bad bits in the factory, at a burn-in test. A fuse bit register in the memory records the address of words including bad bits, as identified during the burn-in test. These addresses are then used to fuse out those words so that other, redundant words are used instead. However, this is often impractical for solving the problem of bad write-error-rate bits. For example, it may require writing and reading every bit 1e9 times during a burn-in test, which would take too long and thus be too expensive.
Thus, there is a need for an improved way to manage bad bits in a memory that overcomes the aforementioned problem.